The content of this course mainly covers two topics：[1] Analog circuit design considerations, including VCO analysis, PLL and parasitic effects and corresponding noise.
[2] Learn to use spectre simulation software to implement electronic circuit theory.
basic course : Electronics circuit , digital logic design
There are assignments for every class, which are regarded as the total semester grade.
此課程內容涵蓋兩個部份:第一部份提供類比電路設計的考量，包括VCO分析、PLL及寄生效應及相對應的雜訊；第二部份藉由學理推導與spectre模擬軟體，探討雜訊對類比效能的影響。本課程旨在導引學生熟悉類比設計與其實務環境，同時深入了解雜訊對類比的效能影響程度，俾提昇學生在類比電路設計實務之專業素養。藉由本課程，學生將會學到類比設計技術及spectre模擬軟體的使用技巧。The content of this course mainly covers two topics: [1] Analog circuit design considerations, including VCO analysis, PLL and parasitic effects and corresponding noise.
[2] Learn to use spectre simulation software to implement electronic circuit theory.
basic course: Electronics circuit, digital logic design
There are assignments for every class, which are regarded as the total semester grade.
This course covers two parts: the first part provides considerations for analog circuit design, including VCO analysis, PLL and parasitic effects and corresponding noise; the second part explores complex circuits through theoretical derivation and Specter simulation software. The impact of information on analog performance. This course aims to guide students to become familiar with analog design and its practical environment, and at the same time gain an in-depth understanding of the impact of noise on analog performance, so as to enhance students' professional quality in analog circuit design practice. Through this course, students will learn analog design technology and the use of Specter simulation software.
鎖相迴路/滄海書局 以及 自編講意
Phase locked loop/Canghai Bookstore and self-edited lectures
| 評分項目 Grading Method | 配分比例 Grading percentage | 說明 Description |
|---|---|---|
| Lab1:Basic logic gate simulationLab1:Basic logic gate simulation Lab1:Basic logic gate simulation |
15 | 作業成績(Homework results) |
| Lab2:Divider simulationLab2:Divider simulation Lab2: Divider simulation |
15 | 作業成績(Homework results) |
| Lab3:RING VCO simulationLab3:RING VCO simulation Lab3:RING VCO simulation |
15 | 作業成績(Homework results) |
| Lab4:CP / PFD simulationLab4:CP / PFD simulation Lab4:CP/PFD simulation |
15 | 作業成績(Homework results) |
| Lab 5 : VCO + DIVIDER + CP/PFD simulationLab 5 : VCO + DIVIDER + CP/PFD simulation Lab 5: VCO + DIVIDER + CP/PFD simulation |
15 | 作業成績(Homework results) |
| Lab 6 : PLL simulationLab 6 : PLL simulation Lab 6: PLL simulation |
25 | 作業成績(Homework results) |
